Flash memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type.
Flash memory devices typically include parallel bit lines, usually contained within the same metal layer within the semiconductor, that are used during the reading and writing operations to select the appropriate memory cell.
FIG. 1 depicts a typical prior art configuration. Bit lines 10, 20, and 30 are roughly parallel and in relatively close proximity to one another. Bit lines 10, 20, and 30 typically are fabricated as part of the same metal layer within the semiconductor die. Bit lines 10, 20, and 30 connect to other circuit components through connectors 40.
FIG. 2 depicts the same prior art configuration from a top view. Again, bit lines 10, 20, and 30 are roughly parallel to one another. Their proximity and length result in parasitic capacitance, which can be modeled as capacitor 15 and capacitor 25.
As flash memory designs become smaller and denser, parasitic capacitance between adjacent bit lines will become more problematic.
What is needed are improved circuit designs that compensate for the parasitic capacitance between bit lines.
What is needed is an improved layout design to reduce the amount of parasitic capacitance in an advanced nanometer flash memory device.